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atmel-42351a-wilc1000-smartconnect-datasheet_092014 description the atmel ? wilc1000 is a single chip ieee ? 802.11 b/g/n iot (i nternet of things) link controller soc. the wilc1000 most advanced mode is a single stream 1x1 802.11n mode providing up to 72mbps phy throughput. the wilc1000 features fully integrated power amplifier, lna, switch and power management. implemented in 65nm cmos technology, the wilc1000 offers very low power consumption while simultan eously providing high perf ormance and opt imized bill of material. the wilc1000 supports 2, 3, and 4 wire bluetooth coexistenc e protocols. the wilc1000 provides multiple peripheral interf aces including uart, spi, i2c, and sdio. the only external clock source needed for the wilc1000 is a high-speed crystal or oscillator with a wide variety of reference clock fr equencies supported (between 12 - 50mhz). the wilc1000 is available in both qfn and wafer level chip scale package (wlcsp) packaging. features ? ieee 802.11 b/g/ n rf/ph/mac soc ? ieee 802.11 b/g/n (1x1 ) for up to 72mbps ? single spatial stream in 2.5ghz rf band ? integrated pa and t/r switch ? superior sensitivity and range vi a advanced phy signal processing ? advanced equalization and channel estimation ? advanced carrier and timing synchronization ? wi-fi direct and soft-ap support ? supports ieee 802.11 we p, wpa, wpa2 security ? supports china wapi security ? superior mac throughput via hardware accelerated two-level a-msdu/a- mpdu frame aggregation and block acknowledgement ? on-chip memory management engine to reduce host load ? spi and sdio host interfaces ? 2/3/4-wire bluetooth co existence interface atmel atwilc1000 single chip ieee 802.11 b/g/n link controller soc preliminary datasheet
atmel atwilc1000a [preliminary datasheet] atmel-42351a-wilc1000-smartconnect-datasheet_092014 2 1. ordering information note: 1. the qfn package is a qualified green package. 2. package information table 2-1. wilc1000 qfn package information (1) note: 1. for the details, see ?package drawing? on page 24 ordering code package (1) description atwilc1000a-mu-t 5x5 qfn single 802.11.b/g/n chip atwilc1000-mr110pa 22 x 15mm certified module with atwilc1000a-mu chip and pcb antenna atwilc1000-sdpro atwilc1000-mr110pa mounted on sd adapter card parameter value units tolerance package size 5 x 5 mm 0.1mm qfn pad count 40 total thickness 0.85 mm 0.05mm qfn pad pitch 0.4 mm pad width 0.2 mm exposed pad size 3.7 x 3.7 mm
3 atmel atwilc1000a [pre liminary datasheet] atmel-42351a-wilc1000-smartconnect-datasheet_092014 3. block diagram figure 3-1. wilc1000 block diagram ; ; 7[ 'ljlwdo &ruh '3' ejq l))7 ejq &rglqj +rvw,qwhu idfh 0lfurfrqwuroohu '$& $ '& 5 [ 'ljlwdo &ruh ejq 2)'0 &kdqqh o (v wlpd wlrq (txd ol]dwlrq ejq )ruzdug (uu r u &ruuhfwlrq 5$0 3/ / e j q 0$& a 8$57 63 , 'hglfdwhg*3,2 :,/& ;2 308 , & 57&&orfn
atmel atwilc1000a [preliminary datasheet] atmel-42351a-wilc1000-smartconnect-datasheet_092014 4 4. pinout the atmel wilc1000 is offered in an exposed pad 40l, qfn package. the package has an exposed paddle that must be connected to the system board ground. table 4-1. wilc1000 qfn pin connectivity pin # pin name pull up/down description 1 tp_p none test pin / customer no connect 2 vdd_rf none tuner 1.2v rf supply 3 rfiop none pos rf differential i/o 4 rfion none neg rf differential i/o 5 paldo_out none n/c. for internal use only 6 vdd_batt none battery supply for pa ldo 7 vdd_ams none 1.2v analog / mixed signal supply 8 efuse_vddq none nc on customer board 9 sdio_spi_cfg none tie to 1 for spi, 0 for sdio 10 gpio0/host_wake programmable pull-up gpio0 / sleep mode control 11 gpio2/irqn programmable pull-up gpio2 / device interrupt 12 sd_dat3 programmable pull-up sdio data3 13 sd_dat2/spi_rxd programmable pull-up sdio data2 / spi data rx 14 vddc none 1.2v core power supply 15 vddio none i/o power supply 16 sd_dat1/spi_ssn programmable pull-up sdio data1 / spi slave select 17 sd_dat0/spi_txd programmable pull-up sdio data0 / spi data tx 18 sd_cmd/spi_sck programmable pull-up sdio command / spi clock 19 sd_clk programmable pull-up sdio clock 20 vbatt_buck none battery supply for dc/dc converter 21 vsw none 1.2v power from dc/dc converter 22 vreg_buck none feeds vsw back to dc/dc converter 23 chip_en none pmu enable 24 gpio1/rtc_clk programmable pull-down gpio1 / 32khz clock input 25 test_mode none test mode - customer tie to gnd 26 vddio none i/o power supply 27 vddc none 1.2v core power supply 28 gpio3 programmable pull-up gpio3 / spi_sck_flash 29 gpio4 programmable pull-up gpio4 / spi_ssn_flash
5 atmel atwilc1000a [pre liminary datasheet] atmel-42351a-wilc1000-smartconnect-datasheet_092014 30 gpio5 programmable pull-down gpio5 / spi_txd_flash 31 gpio6 programmable pull-up gpio6 / spi_rxd_flash 32 i2c_scl programmable pull-up i2c slave clock 33 i2c_sda programmable pull-up i2c slave data 34 resetn none active-low hard reset 35 xo_n none crystal oscillator n 36 xo_p none crystal oscillator p 37 vdd_sxdig none 1.2v sx power supply 38 vdd_vco none 1.2v vco power supply 39 vdda_io none tuner vddio supply 40 tpn none test pin / customer no connect 41 paddle vss none connect to system board ground table 4-1. wilc1000 qfn pin connectivity (continued) pin # pin name pull up/down description
atmel atwilc1000a [preliminary datasheet] atmel-42351a-wilc1000-smartconnect-datasheet_092014 6 5. power management 5.1 power architecture the atmel wilc1000 device uses an innovative power archit ecture to eliminate the need for external regulators and reduce the number of off-chip components. the architecture is shown in figure 5-1 . the power management unit (pmu) has a dc/dc converter that converts vbatt to the 1.2v supply used by the digital and rf/ams blocks. the pa and efuse are su pplied by dedicated ldos, and the vco is supplied by a separate ldo structure. the power connections in figure 5-1 provide a conceptual framework for understanding the wilc1000 power architecture. reference designs will be provided to demonstrate how to prope rly connect the supplies, including proper isolation of the supplies used by the digital and rf/ams blocks. figure 5-1. wilc1000 power architecture 9%$77b%8&. riifkls /& 5)9&ruh n+] 2vf 9 96: 95(* 9''& 9''$06 9''5) 9''6;',* /'2 9'',2 9''9&2 /'2 a 3$ /'2 9''%$77 3$/'2b287 9 9 &+,3b(1 ()86(b9''4 h)xvh /'2 6; 'ljlwdo9&ruh '&'&&rqyhuwhu hqd h)xvh 3$ 308 5)$06 'ljlwdo 9lq 9rxw
7 atmel atwilc1000a [pre liminary datasheet] atmel-42351a-wilc1000-smartconnect-datasheet_092014 5.2 power consumption 5.2.1 description of device states atmel wilc1000 device has several device states: 5.2.2 controlling the device states table 5-1 shows how to switch between the device states using the following: table 5-1. wilc1000 device state control note: 1. the device is idle in on_doze state during passive scan waiting for the beacon signal 5.2.3 restrictions for power_off state when the atmel wilc1000 is in the device state power_ off, there is no power supplie d to the device, i.e., the dc/dc converter output and vddio are both off (at ground potential). in this case, a voltage cannot be applied to the wilc1000 pins because each pi n contains an esd diode from the pi n to supply. this diode will turn on when voltage higher than one diode-drop is supplied to the pin. if a voltage must be applied to the signal pads while the chip is in a low power stat e, the vddio supply must be on, so the sleep state must be used. similarly, to prevent the pin-to-ground diode from turnin g on, do not apply a voltage that is more than one diode- drop below ground to any pin. ? on_transmit ? on_receive ? on_doze ? sleep ? power_off ? device is actively transmitting an 802.11 signal ? device is actively receiving an 802.11 signal ? device is on but is neither transmitting nor receiving ? device is asleep with 1.2v supply off ? device is powered off; vdd_1p2 and vddio are off ? chi_en ? vddio ? device pin (pin #23) used to enable dc/dc converter ? i/o supply voltage from external supply device state chip_en vddio remark power consumption on_transmit vddio on transmitting 172ma @3.3v (18dbm) 149ma @2.5v (14dbm) 117ma @2.0v (10dbm) on_receive vddio on receiving 70ma @3.3v (-90dbm) 65ma @3.3v (-87dbm) on_doze vddio on idle (1) < 1ma sleep gnd on < 4a
atmel atwilc1000a [preliminary datasheet] atmel-42351a-wilc1000-smartconnect-datasheet_092014 8 6. cpu and memory subsystem 6.1 processor the atmel wilc1000 device has a cort us aps3 32-bit processo r with a jtag debug inte rface. this processor performs many of the mac functions, including but not limited to association, authentication, power management, security key management, and msdu aggreg ation/de-aggregation. in addition, the processor provides flexibility for various modes of operation, such as sta and ap modes. 6.2 memory subsystem the aps3 core uses a small boot rom along with a 12 8kb instruction ram and a 64kb data ram. in addition, the device uses a 128kb shared memory which allows the aps3 core to perform various data management tasks on the tx and rx data packets. 6.3 non-volatile memory the atmel wilc1000 device has 256 bits of non-volatile memory (nvm) that can be read by the cpu after device reset. this non-volatile one-time-programmable (otp) memory can be used to store customer-specific parameters, such as the mac address, along with calibrati on information, such as tx power calibration tables.
9 atmel atwilc1000a [pre liminary datasheet] atmel-42351a-wilc1000-smartconnect-datasheet_092014 7. clocking 7.1 crystal oscillator table 7-1. wilc1000 crystal oscillator parameters the block diagram in figure 7-1 (a) shows how the internal crystal oscilla tor (xo) is connecte d to the external crystal. the xo has 5pf internal capacitance on each terminal xo_p and xo_n. to bypass the crystal oscillator with an external reference, an external signal capable of driv ing 5pf can be app lied to the xo_n terminal as shown figure 7-1 (b). figure 7-1. wilc1000 xo connections to crystal when (a) the crystal oscillator is used, an d (b) the crystal oscillator is bypassed table 7-2. wilc1000 bypass clock specification parameter min typical max units crystal resonant frequency 12 32 mhz crystal equivalent series resistance 50 150 ? stability -100 100 ppm :,/& ;2b1 ;2b3 d :,/& ;2b1 ;2b3 e ([whuqdo&orfn parameter conditions min max units comments oscillator frequency 12 32 mhz must be able to drive 5pf load @ desired frequency voltage swing 0.5 1.8 vpp must be ac coupled stability -100 +100 ppm phase noise @ 1khz offset -130 dbc/hz jitter (rms) <1psec based on integrated phase noise spectrum from 1khz to 1mhz
atmel atwilc1000a [preliminary datasheet] atmel-42351a-wilc1000-smartconnect-datasheet_092014 10 7.2 low power oscillator atmel wilc1000 device provides an internally-generated 32khz clock to provide timing information for various sleep functions. in addition, wilc1000 allows for an ex ternal 32khz clock to be provided through pin 24. software selects whether the internal clock or external clock is used.
11 atmel atwilc1000a [pre liminary datasheet] atmel-42351a-wilc1000-smartconnect-datasheet_092014 8. wlan subsystem the wlan subsystem is composed by the media access controller (mac) and the physical layer (phy). the following two subsections describe the mac and phy in detail. 8.1 mac 8.1.1 features the atmel wilc1000 i eee802.11 mac supports the following functions: ? ieee 802.11b/g/n ? ieee 802.11e wmm qos edca/hcca/pcf multiple access categories traffic scheduling ? advanced ieee 802.11n features: ? transmission and reception of aggregated mpdus (a-mpdu) ? transmission and reception of aggregated msdus (a-msdu) ? immediate block acknowledgement ? reduced interframe spacing (rifs) ? support for ieee802.11i and wfa security with key management ? wep 64/128 ? wpa-tkip ? 128-bit wpa2 ccmp (aes) ? support for wapi security ? advanced power management ? standard 802.11 power save mode ? wi-fi alliance wmm-ps (u-apsd) ? psmp ? rts-cts and cts-self support ? supports either sta or ap mode in the infrastructure basic service set mode ? supports independent ba sic service set (ibss) ? built-in programmable processor for future enhancement and standards evolution ? auto-rate control ? mib management 8.1.2 description the atmel wilc1000 mac is designed to operate at low power while providing high data throughput. the ieee 802.11 mac functions are implemented with a combinatio n of dedicated datapath en gines, hardwired control logic, and a low-power, high-efficiency micropro cessor. the combination of dedicated logic with a programmable processor provid es optimal power efficiency and real-time response while prov iding the flexibility to accommodate evolving standards and future feature enhancements. dedicated datapath engines are used to implement data path functions with heavy co mputational. for example, an fcs engine checks the crc of the transmitting and re ceiving packets, and a cipher engine performs all the required encryption and decryption operations for th e wep, wpa-tkip, wpa2 ccmp -aes, and wapi security requirements.
atmel atwilc1000a [preliminary datasheet] atmel-42351a-wilc1000-smartconnect-datasheet_092014 12 control functions which have real-tim e requirements are implemented using hardwired control logic modules. these logic modules offer re al-time response while maintaining configur ability via the processor. examples of hardwired control logic modules are the channel access contro l module (implements edca/hcca, beacon tx control, interframe spacing, etc.), protocol timer mo dule (responsible for the network access vector, back-off timing, timing synchronization function, and slot management), mpdu handling module, aggregation/de- aggregation module, block-ack controller (impleme nts the protocol requirements for burst block communication), and tx/rx control fsms (coordinate data movement between phy-mac interface, cipher engine, and the dma interface to the tx/rx fifos). the mac functions implemented solely in software on the microprocessor have the following characteristics: ? functions with high memory requirements or complex data structures. examples are association table management and power save queuing. ? functions with low computational load or without critical real-time requirements. examples are authentication and association. ? functions which need flexibility a nd upgradeability. examples are b eacon frame processing and qos scheduling. 8.2 phy 8.2.1 features the atmel wilc1000 i eee802.11 phy supports th e following functions: ? single antenna 1x1 stream in 20mhz channels ? supports ieee 802.11b dsss-cck mo dulation: 1, 2, 5.5, 11mbps ? supports ieee 802.11g ofdm modulation: 6, 9, 12 ,18, 24, 36 , 48, 54mbps ? supports ieee 802.11n ht m odulations mcs0-7, 20mhz, 800 and 400ns gu ard interval: 6. 5, 7.2, 13.0, 14.4, 19.5, 21.7, 26.0, 28 .9, 39.0, 43.3, 52.0, 57 .8, 58.5, 65.0, 72.2mbps ? ieee 802.11n mixed mode operation ? per packet tx power control ? advanced channel estimation/equalization, automatic gain control, cca, carrier/symbol recovery, and frame detection 8.2.2 description the atmel wilc1000 phy is designed to achieve relia ble and power-efficient physical layer communication specified by ieee 802.11 b/g/n in si ngle stream mode with 20mhz bandwid th. advanced algorithms have been employed to achieve maximum throughput in a real world communication environment with impairments and interference. the phy implements all the required functi ons such as fft, filtering, fec (viterbi decoder), frequency and timing acquisition and tracking, channel estimation and equalization, carrier sensing and clear channel assessment, as well as the automatic gain control.
13 atmel atwilc1000a [pre liminary datasheet] atmel-42351a-wilc1000-smartconnect-datasheet_092014 8.3 radio 8.3.1 receiver performance table 8-1. wilc1000 receiver performance parameter description min typical max unit frequency 2,412 2,484 mhz sensitivity 802.11b 1mbps dss -98.2 dbm 2mbps dss -94.7 dbm 5.5mbps dss -93.0 dbm 11mbps dss -89.0 dbm sensitivity 802.11g 6mbps ofdm -91.0 dbm 9mbps ofdm -90.0 dbm 12mbps ofdm -88.5 dbm 18mbps ofdm -86.5 dbm 24mbps ofdm -84.0 dbm 36mbps ofdm -80.5 dbm 48mbps ofdm -77.0 dbm 54mbps ofdm -75.0 dbm sensitivity 802.11n (bw = 20mhz) mcs 0 -89.5 dbm mcs 1 -87.5 dbm mcs 2 -85.0 dbm mcs 3 -82.5 dbm mcs 4 -80.0 dbm mcs 5 -75.5 dbm mcs 6 -73.5 dbm mcs 7 -72.0 dbm maximum receive signal level 1-11mbps dss -10 0 dbm 6-54mbps ofdm -10 0 dbm mcs 0 - 7 -10 0 dbm
atmel atwilc1000a [preliminary datasheet] atmel-42351a-wilc1000-smartconnect-datasheet_092014 14 8.3.2 transmitter performance adjacent channel rejection 1mbps dss (30mhz offset) 50 db 11mbps dss (30mhz offset) 43 db 6mbps ofdm (25mhz offset) 40 db 54mbps ofdm (25mhz offset) 25 db mcs 0 - 20mhz bw (25mhz offset) 40 db mcs 7 - 20mhz bw (25mhz offset) 20 db cellular blocker immunity 776-794mhz cdma -14 dbm 824-849mhz gsm -10 dbm 880-915mhz gsm -10 dbm 1710-1785mhz gsm -15 dbm 1850-1910mhz gsm -15 dbm 1850-1910mhz wcdma -24 dbm 1920-1980mhz wcdma -24 dbm table 8-1. wilc1000 receiver performance (continued) parameter description min typical max unit table 8-2. wilc1000 transmitter performance parameter description min typical max unit frequency 2,412 2,484 mhz output power 802.11b dsss 1mbps 20.6 (1) dbm 802.11b dsss 11mbps 20.6 (1) dbm 802.11g ofdm 6mbps 20.5 (1) dbm 802.11g ofdm 54mbps 17.8 (1) dbm 802.11n ht20 mcs 0 18.8 (1) dbm 802.11n ht20 mcs 7 15.3 (1) dbm tx power accuracy 1.5 (2) db carrier suppression 30.0 dbc
15 atmel atwilc1000a [pre liminary datasheet] atmel-42351a-wilc1000-smartconnect-datasheet_092014 notes: 1. measured at 802.11 spec compliant evm / spectral mask 2. without calibration 8.3.3 calibration atmel wilc1000 device does not require any external ca libration to meet the specifications shown in this document. the wilc1000 does however contain nonv olatile memory for customer's optional use. ? frequency compensation - improve frequency accuracy of main system clock based on external crystal ? power control - improve output power toleranc e beyond limits specified in this document ? mac address programming sensitivity 802.11g 76-108 -125 dbm/hz 776-794 -125 dbm/hz 869-960 -125 dbm/hz 925-960 -125 dbm/hz 1570-1580 -125 dbm/hz 1805-1880 -125 dbm/hz 1930-1990 -125 dbm/hz 2110-2170 -125 dbm/hz harmonic output power 2 nd -33 dbm/mhz 3 rd -38 dbm/mhz table 8-2. wilc1000 transmitter performance (continued) parameter description min typical max unit
atmel atwilc1000a [preliminary datasheet] atmel-42351a-wilc1000-smartconnect-datasheet_092014 16 9. external interfaces atmel wilc1000 external interfaces include i 2 c for control, spi and sdio for control and data transfer, seven general purpose input / output (gpio) pins, and a wi-fi / bluetooth coexistence interface. 9.1 i 2 c interface 9.1.1 overview atmel wilc1000 provides an i 2 c bus slave that allows the host processo r to read or write any register in the chip. the wilc1000 supports i 2 c bus version 2.1 - 2000. the i 2 c interface, used primarily for contro l, is a two-wire serial interface consisting of a serial data line (sda, pin 33) and a serial clock (scl, pin 32). it responds to the seven bit address value 0x60. the wilc1000 i2c interface can operate in standard mode (with data rates up to 100kb/s) and fast mode (with data rates up to 400kb/s). the i 2 c is a synchronous serial interface. the sda line is a bidirectional signal and changes only while the scl line is low, except for stop, start, and restart cond itions. the output drivers are open-drain to perform wire-and functions on the bus. the maximum number of devices on the bus is limited by only the maximum capacitance specification of 400pf. da ta is transmitted in byte packages. for specific informat ion, please refer to the philip s specification entitled "the i 2 c -bus specification, version 2.1". 9.1.2 i 2 c timing the i 2 c is provided in figure 9-1 and in table on page 17 . figure 9-1. wilc1000 i 2 c timing diagram w +/ 6'$ 6&/ w +'67$ w :/ w :+ w 68'$7 w 35 w +''$7 w 35 w 35 w /+ w +/ w /+ w 68672 w %8) w 6867$ i 6&/
17 atmel atwilc1000a [pre liminary datasheet] atmel-42351a-wilc1000-smartconnect-datasheet_092014 9.2 spi interface 9.2.1 overview atmel wilc1000 device has a serial peri pheral interface (spi) that operates as a spi slave. the spi interface can be used for control and for serial i/o of 802.11 da ta. the spi pins are mapped as shown in table 12. the spi is a full-duplex slave-synchronous serial interface th at is available immediately following reset when pin 9 (sdio_spi_cfg) is tied to vddio. table 9-2. wilc1000 spi interface pin mapping when the spi is not selected, i.e., when ssn is high , the spi interface will not interfere with data transfers between the serial-master and other serial-slave devices. when the serial slave is not selected, its transmitted data output is buffered, resulting in a high impe dance drive onto the serial master receive line. the spi interface responds to a protocol that allows an external host to read or write any register in the chip as well as initiate dma transfers. table 9-1. wilc1000 i 2 c timing parameters parameter symbol min max units remarks scl clock frequency f scl 0 400 khz scl low pulse width t wl 1.3 s scl high pulse width t wh 0.6 s scl, sda fall time t hl 300 ns scl, sda rise time t lh 300 ns this is dictated by external components start setup time t susta 0.6 s start hold time t hdsta 0.6 s sda setup time t sudat 100 ns sda hold time t hddat 0 ns slave and master default 40 ns master programming option stop setup time t susto 0.6 s bus free time between stop and start t buf 1.3 s glitch pulse reject t pr 0 50 ns pin # spi function 9 cfg: must be tied to vddio 16 ssn: active low slave select 13 rxd: serial data receive 18 sck: serial clock 17 txd: serial data transmit
atmel atwilc1000a [preliminary datasheet] atmel-42351a-wilc1000-smartconnect-datasheet_092014 18 9.2.2 spi timing the spi timing is provided in figure 9-2 and in table on page 18 figure 9-2. wilc1000 spi timing diagram table 9-3. wilc1000 spi slave timing parameters parameter symbol min max units clock input frequency f sck 48 mhz clock low pulse width t wl 15 ns clock high pulse width t wh 15 ns clock rise time t lh 10 ns clock fall time t hl 10 ns input setup time t isu 5 ns w /+ 6&. 7;' 5;' 661 w :+ w +/ w :/ w 2'/< w ,68 w ,+' i 6&. w 662'/< 661 w 68661 w +'661 63,0dvwhu 63,6odyh
19 atmel atwilc1000a [pre liminary datasheet] atmel-42351a-wilc1000-smartconnect-datasheet_092014 9.3 wi-fi / bluetooth coexistence atmel wilc1000 device supports 2-wire, 3-wire, and 4-wi re wifi/bluetooth coexistence algorithms. as shown in table 9-4 , the 2-wire interface uses gpio3 and gpio4, the 3-wire interface uses gpio3, gpio4, and gpio5, and the 4-wire interface uses gpio3, gpio4, gpio5, and gpio6. table 9-4. wilc1000 coexistence pins 9.4 sdio interface 9.4.1 features ? meets sdio card specification version 2.0 ? host clock rate variable between 0 and 50mhz ? 1 bit/4-bit sd bus modes supported ? allows card to interrupt host ? responds to direct read/wri te (io52) and extended read/write (io53) transactions ? supports suspend/resume operation 9.4.2 description the wilc1000 sdio is a full speed interface. the interface supports the 1-bit/4-bit sd transfer mode at the clock range of 0-50mhz. the host can use this interface to read and write from any register within the chip as well as configure the wilc1000 for data dma. to use th is interface, pin 9 (sdio_ spi_cfg) must be grounded. the sdio pins are mapped as shown in table . input hold time t ihd 5 ns output delay t odly 0 20 ns slave select setup time t sussn 5 ns slave select hold time t hdssn 5 ns table 9-3. wilc1000 spi slave timing parameters parameter symbol min max units pin name pin # 2-wire 3-wire 4-wire gpio3 28 not used used used gpio4 29 used used used gpio5 30 used used used gpio6 31 not used not used not used table 9-5. wilc1000 sdio interface pin mapping pin # spi function 9 cfg: must be tied to ground 12 dat3: data 3 13 dat2: data 2
atmel atwilc1000a [preliminary datasheet] atmel-42351a-wilc1000-smartconnect-datasheet_092014 20 when the sdio card is inserted into an sdio aware host, the detection of the ca rd will be via the means described in sdio specification. duri ng the normal initialization and interrogation of the card by the host, the card will identify itself as an sdio device. the host software will obtain the card information in a tuple (linked list) format and determine if that card's i/o function(s) are acce ptable to activate. if the ca rd is acceptable, it will be allowed to power up fully and start the i/o function(s) built into it. the sd memory card communication is based on an ad vanced 9-pin interface (clock, command, 4 data and 3 power lines) designed to operate at ma ximum operating frequency of 50mhz. 9.4.3 sdio timing figure 9-3. wilc1000 sd io timing diagram 16 dat1: data 1 17 dat0: data 0 18 cmd: command 19 clk: clock table 9-5. wilc1000 sdio interface pin mapping (continued) pin # spi function table 9-6. wilc1000 sdio timing parameters parameter symbol min max units clock input frequency f pp 0 50 mhz clock low pulse width t wl 10 ns clock high pulse width t wh 10 ns clock rise time t lh 10 ns clock fall time t hl 10 ns 6'b&/. ,qsxwv 2xwsxwv i ss w :/ w :+ w +/ w /+ w ,68 w ,+ w 2'/<0$; w 2'/<0,1
21 atmel atwilc1000a [pre liminary datasheet] atmel-42351a-wilc1000-smartconnect-datasheet_092014 9.5 gpios seven general purpose input / output (g pio) pins are available to allow for application specific functions. each gpio pin can be programmed as an input (the value of the pin can be read by the host or internal processor) or as an output (the output values can be programmed by the host or internal processor), where the default mode after power-up is input. input setup time t isu 5 ns input hold time t ih 5 ns output delay t odly 0 14 ns table 9-6. wilc1000 sdio timing parameters (continued) parameter symbol min max units
atmel atwilc1000a [preliminary datasheet] atmel-42351a-wilc1000-smartconnect-datasheet_092014 22 10. electrical characteristics 10.1 absolute maximum ratings table 10-1. absolute maximum ratings notes: 1. v ain is for the following analog pins: vdd_rf, rfiop, rfion, vdd_ams, xo_n, xo_p, vdd_sxdig, vdd_vco 2. for v esdhbm , each pin is classified as class1 or class2 ? the class1 pins are: tp_p, vdd_rf, rfiop, rfio n, paldo_out, vdd_batt , vdd_ams, efuse_vddq, vbatt_buck, vsw, vreg_buck, chip_en, xo_n, xo_p, vd d_sxdig, vcc_vco, vdda_io, tpn. all others are class2 pins. ? v esdhbm is 1kv for class1 pins. v esdhbm is 2kv for class2 pins. 10.2 recommended operating conditions table 10-2. recommended operating conditions note: 1. the atmel wilc1000 is functional across this range of vo ltages; however, optimal rf performance is guaranteed for vbatt in the range 3.0v < vbatt < 4.2v. symbol parameter min max unit vdd_1p2 1.2v supply voltage -0.3 1.5 v vddio i/o supply voltage -0.3 3.6 v vbatt battery supply voltage -0.3 6.0 v v in digital input voltage -0.3 vddio+0.3 (up to 3.6) v v ain (1) analog input voltage -0.3 v v esdhbm (2) esd human body model -1000, -2000 +1000, +2000 v t a storage temperature -65 150 ? c junction temperature 125 ? c rf input power max 16 dbm symbol parameter min typical max unit vdd_1p2 1.2v supply voltage 1.235 1.3 1.356 v vddio l i/o supply voltage low range 1.62 1.8 1.98 v vddio m i/o supply voltage mid range 2.25 2.50 2.75 v vddio h i/o supply voltage high range 3.00 3.30 3.60 v vbatt battery supply voltage 2.5 (1) 3.6 4.2 v operating temperature -20 85 ? c
23 atmel atwilc1000a [pre liminary datasheet] atmel-42351a-wilc1000-smartconnect-datasheet_092014 10.3 dc characteristics the table 10-3 provides the dc characteristics for the digital pads. table 10-3. recommended operating conditions vddio condition min max unit vddio l input low voltage v il -0.30 0.63 v input high voltage v ih 1.17 vddio+0.30 v output low voltage v ol 0.45 v output high voltage v oh 1.35 v vddio m input low voltage v il -0.30 0.70 v input high voltage v ih 1.70 vddio+0.30 v output low voltage v ol 0.70 v output high voltage v oh 1.70 v vddio h input low voltage v il -0.30 0.80 v input high voltage v ih 2.00 vddio+0.30 (up to 3.60) v output low voltage v ol 0.40 v output high voltage v oh 2.40 v all output loading 20 pf all digital input load 6 pf
atmel atwilc1000a [preliminary datasheet] atmel-42351a-wilc1000-smartconnect-datasheet_092014 24 11. package drawing 11.1 40qfn 5x5 figure 11-1. qfn package drawing d/e ekd dy x? x? x x? ? x? x ? x? x? x?? ? ?x ?x ?x? ? ?x ?x ?x? x?? xe xe? z x? v xe? e d/>>/ddz ^zdk> x?z& ?x? ?x? ?
25 atmel atwilc1000a [pre liminary datasheet] atmel-42351a-wilc1000-smartconnect-datasheet_092014 12. technical support and resources for ? technical ? support ? visit: ? http://www.atmel.com/design \ support
atmel atwilc1000a [preliminary datasheet] atmel-42351a-wilc1000-smartconnect-datasheet_092014 26 13. revision history doc. rev. date comments 42351a 09/2014 initial document release.
i atmel wilc1000a [preliminary datasheet] atmel-42351a-atwilc1000a-smartconnect-datasheet_092014 table of contents description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4. pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5. power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5.1 power architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5.2 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6. cpu and memory subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.1 processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.2 memory subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.3 non-volatile memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7. clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.1 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.2 low power oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8. wlan subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 8.1 mac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 8.2 phy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8.3 radio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 9. external interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 9.1 i2c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 9.2 spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9.3 wi-fi / bluetooth coexistence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9.4 sdio interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9.5 gpios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 10. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 10.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 10.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 10.3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 11. package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 11.1 40qfn 5x5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 12. technical support and resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 13. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
x x xx x x atmel corporation 1600 technology drive, san jose, ca 95110 usa t: (+1)(408) 441.0311 f: (+1)(408) 436.4200 | www.atmel.com ? 2014 atmel corporation. / rev.: atmel-42351a-atwilc1000a-smartconnect-datasheet_092014. atmel ? , atmel logo and combinations thereof, enabling unlimited possibilities ? , and others are registered trademarks or trademarks of atmel corporation in u.s. and other countries. other terms and product names may be trademarks of others. disclaimer: the information in this document is provided in c onnection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in the atmel terms and condit ions of sales located on the atmel website, atmel assumes no liability wh atsoever and disclaims any express, implied or statutory warranty relating to its p roducts including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, pu nitive, special or incidental damages (including, without limi tation, damages for loss and profits, business interruption, or loss of information ) arising out of the use or inability to use this document, even if atmel has been advised of the possibility of such damages. atmel makes no r epresentations or warranties with respect to the accuracy or c ompleteness of the contents of this document and reserves the right to make changes to specificatio ns and products descriptions at any time without notice. atmel d oes not make any commitment to update the information contained herein. unless specifically provided otherwise, atme l products are not suitable for, and shall not be used in, automo tive applications. atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. safety-critical, military, and automotive applications disclaim er: atmel products are not designed for and will not be used in connection with any applications where the failure of such products would reasonably be expected to re sult in significant personal inju ry or death (?safety-critical a pplications?) without an atmel officer's specific written consent. safety-critical applications incl ude, without limitation, life support devices and systems, equipment or systems for t he operation of nuclear facilities and weapons systems. atmel products are not designed nor intended for use in military or aerospace applications or environments unless specifically designated by atmel as military- grade. atmel products are not designed nor intended for use in automot ive applications unless spec ifically designated by atmel as automotive-grade.

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